The increased computing power of each generation of electronic systems has given rise to the need for semiconductor memory devices of greater and greater storage density. Storage density refers the amount of data that can be stored in a given area on a semiconductor substrate. Because integrated circuits are typically manufactured by forming multiple die on a semiconductor wafer, in general, the higher the density of the design, the more economical it is to produce the integrated circuit. This can apply not only to "standalone" semiconductor memory devices (those devices whose only function is the storage of data), but also to devices having "embedded" memory as well. Embedded memory is a section of memory that is included on a larger integrated circuit. Embedded higher density semiconductor memory designs also free up more area on the larger integrated circuit, allowing for greater flexibility in design and/or added features.
A preferred type of semiconductor memory device, due to its high density and relatively low power consumption characteristics, is the dynamic random access memory (DRAM). Because of this, any practical approaches to improving DRAM density could benefit a great number of electronic systems.
Conventional DRAM architectures are well known. A DRAM will typically include an array of memory cells that are coupled to bit lines by the activation of word lines. The DRAM will further include a number of sense amplifiers, each of which amplifies a differential signal at its two inputs. The inputs of each sense amplifier are coupled to bit lines, and in any active operation, one input will be coupled to a bit line carrying a data signal while the other input will be coupled to a reference signal. A data signal that is greater than the reference signal will be amplified to generate one logic value (a logic "1" for example), while a data signal that is less than the reference signal will be amplified to generate another logic value (a logic "0" for example).
DRAMs architectures include "open" bit line architectures as well as "folded" bit line architectures. Typical open bit line architectures are utilized in dense memory cell arrangements, where the activation of a word line results in data being placed on adjacent bit lines. In such applications the reference signal is often generated by a "dummy" memory cell. A drawback to open bit line architectures is the susceptibility of such architectures to noise. Such noise can limit the size of the bit lines or cell capacitors, and/or require additional sense amplifiers. For this reason, open bit line architectures are usually avoided.
Folded bit line architectures reduce the adverse effects of noise. In a folded bit line architecture, adjacent bit lines each form a folded bit line pair. Each folded bit line pair is coupled as the inputs to a differential-type sense amplifier. When a word line is activated, data is placed on one bit line of the bit line pair but not on the other bit line of the bit line pair. This allows the adjacent bit line to carry a reference signal. By using adjacent bit lines (which have the same general dimensions and are made of the same material) the majority of the noise will be common mode noise, and can be rejected by the sense amplifier.
An example of a prior art folded bit line DRAM memory array arrangement is set forth in FIGS. 1A-1E. The prior art folded bit line DRAM array is composed of a number of memory cells, two of which are set forth in FIG. 1A. The memory cells are designated by the general reference characters 100a and 100b, and in the view of FIG. 1A, are shown to be formed in an active area 102 that is surrounded by an insulation region 104. Each of the memory cells (100a and 100b) includes an associated word line (106a and 106b) created over the active area 102 to thereby form a metal-oxide-semiconductor (MOS) transistor. The memory cells (100a and 100b) share a common bit line contact 108 that is formed between the word lines (106a and 106b).
The memory cells (100a and 100b) set forth in FIG. 1A are often referred to as "8F.sup.2 " memory cells, because of the area occupied by each memory cell. For a given semiconductor device manufacturing process, given a minimum feature size, shown as "F," the area formed by each memory cell is a rectangle having sides of 4F and 2F. The memory cell pair (100a and 100b) will thus occupy 16F.sup.2.
To assist in understanding the arrangement of the various embodiments set forth herein, a prior art memory cell array utilizing 8F.sup.2 memory cells will be described in a series of top plan views in FIGS. 1B to 1E. FIGS. 1B to 1E all set forth a portion of a DRAM array with the area of memory cell pairs being delineated with a bold dashed line. Each view illustrates a different set of layers. FIG. 1B illustrates the word lines (110a-110h) and bit line contacts as set forth in FIG. 1A. Only selected of the bit line contacts are identified by the reference character 112 to avoid cluttering the view of FIG. 1B. In addition, storage node contacts for each memory cell are also set forth. For the same reasons, only selected of the storage contacts are identified by the reference character 114. The storage node contacts 114 connect the transistors formed within the substrate to storage capacitors that are disposed above the substrate. The bit lines contacts 112 connect bit lines to the substrate.
FIG. 1C is a top plan view illustrating additional layers formed on top of those set forth in FIG. 1B. Included are local bit lines (116a-116c) and storage nodes. Selected storage nodes are shown as items 118. In addition, for reference, the bit line contacts 112 have been carried over from FIG. 1B. The storage node arrangement of FIG. 1C describes a "capacitor-under-bit line" (CUB) arrangement. Thus, prior to the formation of the bit line contacts 112, the storage nodes 118 are formed. It is understood that the storage nodes 118 function as one plate of a storage capacitor. Accordingly, subsequent to their formation, a capacitor dielectric will be formed over the storage nodes 118, which will then be covered by a capacitor plate common to all of the storage capacitors.
The local bit lines (116a-116c) of FIG. 1C are shown to extend over the substrate, perpendicular to the word lines (110a-110h). The local bit lines (116a-116c) make contact to each of the memory cell pairs at the corresponding the bit line contacts 112.
FIG. 1D is the same top plan view as FIG. 1C, but illustrates a different capacitor configuration. Instead of a CUB type arrangement, FIG. 1C illustrates the case of a capacitor-over-bit line (COB) arrangement. Thus, while FIG. 1D includes the same bit line (116a-116c) and bit line contact 112 arrangement, COB type storage nodes, selected of which are shown as items 120 are also set forth. As in the case of FIG. 1C, a capacitor dielectric and a common plate are formed over the storage nodes 120.
FIG. 1E illustrates how a "global" bit lines (122a-122c) are formed over the local bit lines (116a-116c). The "global" bit lines (122a-122c) are typically made from a lower resistance material than the local bit lines (116a-116c). Data signals on the local bit lines (116a-116c) may be coupled to corresponding global bit lines (122a-122c) by way of bit line select circuits (not shown in FIGS. 1A-1E).
FIGS. 1A-1E can also be instructive to illustrate additional concerns that arise in the manufacture of integrated circuits. If the conductive layers required to form the storage capacitors (i.e., the storage node and the common plate) are discounted, three conductive layers are required to form the memory cell array. The first conductive layer forms the word lines (110a-110h), and may be doped polysilicon. The second layer forms the local bit lines (116a-116c), and may be doped polysilicon or a metal layer. The third layer forms the global bit lines (122a-122c), and may be formed from a metallization layer. The fewer number of conductive layers that are required to manufacture a device, the less expensive and higher yielding (having fewer defects) the device can be. Thus, it is desirable to use as few conductive layers as possible to arrive at the most compact and noise resistant design possible.
U.S. Pat. No. Re. 33,694 reissued to David J. McElroy on Sep. 17, 1991 and titled DYNAMIC MEMORY ARRAY WITH SEGMENTED BIT LINES, sets forth a DRAM having a memory cell array with segmented bit lines. As best shown in FIG. 5 of McElroy, the DRAM includes bit lines (33) that are coupled to bit line segments (87) by transistors (88). While McElroy reduces some effects of noise by utilizing folded bit lines (33), a drawback to the approach of McElroy is the capacitance presented by the bit lines (33). The charge provided by the storage capacitors (85) must be capable of creating a differential voltage not only a bit line segment (87), but also on the entire bit line (33) as well. This may limit how many memory cells can be connected to the bit line segments (87) and the maximum length of the bit lines (33). In addition, McElroy utilizes dummy memory cells (91/90) requiring additional area and the use of dummy word lines (92).
U.S. Pat. No. 5,034,920 issued to Robert N. Rountree on Jul. 23, 1991 and titled CROSS POINT ARRAY MEMORY DEVICE, sets forth a DRAM array that allows for high density memory cell arrangements, such as those found in conventional open bit line architectures, while at the same time reducing the noise effects associated with open bit line arrays. The approach of Rountree is best understood with reference to FIG. 3 of the patent. The array (41) includes partial bit lines or second portions (48, 56, 50 and 58) that are coupled to memory cells (40-1-1 to 40-4-4). Memory cells of adjacent second portions (for example memory cells 40-4-1 and 40-3-1) are accessed by the same word line (64-5). However, unlike a conventional open bit line arrangement, each second portion (48, 56, 50 and 58) is coupled to its associated sense amplifier (42 and 44) by a first portion (46, 54, 52 and 60). Adjacent first portions (for example 54 and 60) have the advantages of folded bit lines as they can be formed parallel to one another, and made with identical dimensions and materials. Like McElroy, a memory cell must be capable of creating a differential voltage signal on a second portion (48, 56, 50 or 58) and its associated first portion (46, 54, 52 or 60). This may limit how many memory cells may be coupled to the second portions (48, 56, 50 or 58) and/or the overall length of the first portions (46, 54, 52 or 60).
Another variation of a DRAM array is set forth in "A 4Mb DRAM with Cross-point Trench Transistor Cell" 1986 IEEE International Solid-State Circuits Conference (ISSCC 1986) by Ashwin H. Shah et al. FIG. 2 of the Shah et al. article illustrates what is referred to as a "Double-Ended Adaptive Folded (DEAF) bit line scheme. The DEAF bit line scheme includes segmented bit lines coupled to memory cells in such a manner, that the activation of a word line will couple adjacent memory cells to adjacent segmented bit lines. A selected pair of segmented bit lines is then connected to a pair of global bit lines by segment select switches. The DEAF bit line scheme further includes a number of section select switches that will, in any given access, divide the global bit lines into a left pair of global bit lines and a right pair of global bit lines. Both the left and right pairs will then include one global bit line portion coupled to a segmented bit line and another coupled to a dummy memory cell.
One possible drawback to the DEAF bit line scheme of the Shah et al. article is the lack of balance in the capacitance seen by the inputs of the sense amplifiers. As just one example, in the access illustrated by FIG. 2, the section select 2 switches are active and the section select 1 switches are inactive. The left sense amplifier will have one input that sees the capacitance of a small global bit line section and a segmented bit line, while the other input will see the capacitance of only a small global bit line section. The right sense amplifier will have one input that sees the capacitance of two global bit line sections and another input that sees the capacitance of one global bit line section and one segmented bit line. The scheme of the Shah et al. article also utilizes dummy memory cells, and so includes the drawbacks of such an approach referred previously.
U.S. Pat. No. 4,800,525 issued to Ashwin H. Shah et al. on Jan. 24, 1989 and titled DUAL ENDED FOLDED BIT LINE ARRANGEMENT AND ADDRESSING SCHEME sets forth a bit line scheme that resembles the DEAF bit line scheme of the Shah et al. ISSCC article. Referring now to FIG. 5 of the Shah et al. patent, the Shah et al. patent is shown to include segment lines (52), each coupled to a number of bit lines shown as BL1 and BL2. Like the ISSCC 1986 article, section switches are used to divide the bit lines (BL1 and BL2) into a left section pair and a right section pair. The lack of balanced capacitance present in the scheme of the ISSSCC 1986 article is addressed in the Shah et al. patent by the utilization of dummy segments (56). The activation of dummy segments (56) results in both inputs to the sense amplifier inputs seeing a similar capacitance. One input will see the capacitance of a certain bit line length (BL1 or BL2) and a segment line (32), while the other input will see the same bit line length (BL1 or BL2) and a dummy segment (56). A drawback to such an approach is the additional area required for the dummy segments. Further, the Shah et al. patent utilizes dummy word lines and dummy memory cells, requiring additional space within the array.
It would be desirable to arrive at a semiconductor memory device having a dense memory cell array that does not present the drawbacks of the prior art. It would further be desirable to arrive at such a dense memory cell array without the necessity of additional metallization layers.